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• The simplest transistor dc bias configuration.

• For dc analysis, open all the capacitance.

DC Analysis

• Applying KVL to the input loop:

VCC = IBRB + VBE

• From the above equation, deriving for IB, we get,

IB = [VCC – VBE] / RB

• The selection of RB sets the level of base current for the operating point.

• Applying KVL for the output loop:

VCC = ICRC + VCE

• Thus,

VCE = VCC – ICRC

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• In circuits where emitter is grounded,

VCE = VE

VBE = VB

Design and Analysis

• Design: Given – IB, IC , VCE and VCC, or IC , VCE and β , design the values of RB,

RC using the equations obtained by applying KVL to input and output loops.

• Analysis: Given the circuit values (VCC, RB and RC), determine the values of IB,

IC , VCE using the equations obtained by applying KVL to input and output loops.

Problem – Analysis

Given the fixed bias circuit with VCC = 12V, RB = 240 kΩ, RC = 2.2 kΩ and β = 75.

Determine the values of operating point.

Equation for the input loop is:

IB = [VCC – VBE] / RB where VBE = 0.7V,

thus substituting the other given values in the equation, we get

IB = 47.08uA

IC = βIB = 3.53mA

VCE = VCC – ICRC = 4.23V

• When the transistor is biased such that IB is very high so as to make IC very high

such that ICRC drop is almost VCC and VCE is almost 0, the transistor is said to be

in saturation.

IC sat = VCC / RC in a fixed bias circuit.

Verification

• Whenever a fixed bias circuit is analyzed, the value of ICQ obtained could be

verified with the value of ICSat ( = VCC / RC) to understand whether the transistor is

in active region.

• In active region,

ICQ = ( ICSat /2)

Load line analysis

A fixed bias circuit with given values of VCC, RC and RB can be analyzed ( means,

determining the values of IBQ, ICQ and VCEQ) using the concept of load line also.

Here the input loop KVL equation is not used for the purpose of analysis, instead, the

output characteristics of the transistor used in the given circuit and output loop KVL

equation are made use of.

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• The method of load line analysis is as below:

1. Consider the equation VCE = VCC – ICRC This relates VCE and IC for the given IB

and RC

2. Also, we know that, VCE and IC are related through output characteristics

We know that the equation,

VCE = VCC – ICRC

represents a straight line which can be plotted on the output characteristics of the

transistor.

Such line drawn as per the above equation is known as load line, the slope of which is

decided by the value of RC ( the load).

Load line

• The two extreme points on the load line can be calculated and by joining which

the load line can be drawn.

• To find extreme points, first, Ic is made 0 in the equation: VCE = VCC – ICRC .

This gives the coordinates (VCC,0) on the x axis of the output characteristics.

• The other extreme point is on the y-axis and can be calculated by making VCE = 0

in the equation VCE = VCC – ICRC which gives IC( max) = VCC / RC thus giving the

coordinates of the point as (0, VCC / RC).

• The two extreme points so obtained are joined to form the load line.

• The load line intersects the output characteristics at various points corresponding

to different IBs. The actual operating point is established for the given IB.

Q point variation

As IB is varied, the Q point shifts accordingly on the load line either up or down

depending on IB increased or decreased respectively.

As RC is varied, the Q point shifts to left or right along the same IB line since the

slope of the line varies. As RC increases, slope reduces ( slope is -1/RC) which

results in shift of Q point to the left meaning no variation in IC and reduction in VCE .

Thus if the output characteristics is known, the analysis of the given fixed bias circuit

or designing a fixed bias circuit is possible using load line analysis as mentioned

above.