We wish to
design a 4-bit multiplexer. The block diagram is given in Fig. 9. There are 4
input data
bits D0{D3, 2 input address bits A0 and A1, one serial output data bit Q, and
We need m
address bits to specify 2m data bits. So in our example, we have 2 address
bits. The
truth table for our decoder is straightforward:
given
For the
\gates/switches" part of the MUX, the design depends upon whether the
input
data lines
carry digital or analog signals. We will discuss the analog possibility later.
The
digital case
is the usual and simplest case. Here, the data routing can be accomplished
simply by
forming 2-input ANDs of the decoder outputs with the corresponding data input,and then
forming an OR of these terms. Explicitly,
Q = C0D0+ C1D1+C2D2+C3D3
Finally, if
an ENABLE line E is included, it is simply ANDed with the righthand side of
this expression.
This can be used to switch the entire MUX IC off/on, and is useful for expansion to more
bits.
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