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8086 Microprocessors & Peripherals

Posted by AJ On Monday, 15 July 2013 0 comments

Microprocessor:
It is a semiconductor device consisting of electronic logic circuits manufactured
by using either a Large scale (LSI) or Very Large Scale (VLSI) Integration Technique. It
includes the ALU, register arrays and control circuits on a single chip.
The microprocessor has a set of instructions, designed internally, to manipulate
data and communicate with peripherals. This process of data manipulation and
communication is determined by the logic design of the microprocessor called the
architecture.
The era microprocessors in the year 1971, the Intel introduced the first 4-bit
microprocessor is 4004. Using this the first portable calculator is designed. The following
table1 shows the list of Intel microprocessors.
Table 1

The different manufacturing companies are introduced different bit size microprocessors
in the past decade is shown in the table 2
Table 2

A microcomputer system just as any other computer system, include two principal
components Hardware and Software. The hardware is a course the circuitry, cabinetry etc
and the software is the collection of programs which direct the computer while it
performs its tasks.
The memory is used to store both data and instructions that are currently being
used. It is normally broken into several modules, each module containing several
thousand locations. Each location may contain part or all of a datum or instruction and is
associated with an identifier called a memory address. The CPU does its work by
successfully inputting, or fetching instructions from memory and carrying out the tasks
detected them.


Figure1.1 shows block diagram of a simple microcomputer. The major parts are
the central processing unit or CPU, memory and the input and output circuitry or
Input/output. Connecting these parts are three sets of parallel line is called buses and
control bus. In a microcomputer the CPU is a microprocessor and is often referred to as
the microprocessor unit (MPU). Its purpose is to decode the instruction and use them to
control the activity with in the system. It performs all arithmetic and logical

computations.

COUNTERS

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 Counter is a register which counts the sequence in binary form.
 The state of counter changes with application of clock pulse.
 The counter is binary or non-binary.
 The total no. of states in counter is called as modulus.
 If counter is modulus-n, then it has n different states.
 State diagram of counter is a pictorial representation of counter states directed by
arrows in graph.

 4-bit Binary Ripple Counter

 All Flip-Flops are in toggle mode.
 The clock input is applied.
 Count enable = 1.
 Counter counts from 0000 to 1111.

Synchronous Binary Counter

 The clock input is common to all Flip-Flops.
 The T input is function of the output of previous flip-flop.
 Extra combination circuit is required for flip-flop input.

REGISTERS

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 Register is a group of Flip-Flops.
 It stores binary information 0 or 1.
 It is capable of moving data left or right with clock pulse.
 Registers are classified as
 Serial-in Serial-Out
 Serial-in parallel Out
 Parallel-in Serial-Out
 Parallel-in parallel Out

 Parallel-in Unidirectional Shift Register

 Parallel input data is applied at IAIBICID.
 Parallel output QAQBQCQD.
 Serial input data is applied to A FF.
 Serial output data is at output of D FF.
 L/Shift is common control input.
 L/S = 0, Loads parallel data into register.
 L/S = 1, shifts the data in one direction

Universal Shift Register

 Bidirectional Shifting.
 Parallel Input Loading.
 Serial-Input and Serial-Output.
 Parallel-Input and Serial-Output.
 Common Reset Input.
 4:1 Multiplexer is used to select register operation.

Master slave SR Flip-Flop

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 Two SR Flip-Flop, 1st is Master and 2nd is slave.
 Master Flip-Flop is positive edge triggered.
 Slave Flip-Flop is negative edge triggered.
 Slave follows master output.
 The output is delayed.

Gated D Latch

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 D Flip-Flop is Data Flip-Flop.
 D Flip-Flop stores 1 or 0.
 R input is complement of S.
 Only one D input is present.
 D Flip-Flop is a storage device used in register

JK Flip-Flop by using SR Flip-Flop

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In SR FF, S=R=1 condition is not allowed.
 JK FF is modified version of SR FF.
 Due to feedback from output to input AND Gate J=K=1 is toggle condition for JK FF.
 The output is complement of the previous output.
 This condition is used in counters.
 T-FF is modified version of JK FF in which T=J=K=1.

Gated SR Latch

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 Enable input C is clock input.
 C=1, Output changes as per input condition.
 C=0, No change of state.
 S=1, R=0 is set condition for Flip-flop.
 S=0, R=1 is reset condition for Flip-flop.
 S=R=1 is ambiguous state, not allowed.

A 4-bit MUX Design

Posted by AJ On Friday, 12 July 2013 0 comments

We wish to design a 4-bit multiplexer. The block diagram is given in Fig. 9. There are 4

input data bits D0{D3, 2 input address bits A0 and A1, one serial output data bit Q, andan (optional) enable bit E which is used for expansion (discussed later). First we will design the decoder
We need m address bits to specify 2m data bits. So in our example, we have 2 address
bits. The truth table for our decoder is straightforward:
 The implementation of the truth table with standard gates is also straightforward, as
given
For the \gates/switches" part of the MUX, the design depends upon whether the input
data lines carry digital or analog signals. We will discuss the analog possibility later. The
digital case is the usual and simplest case. Here, the data routing can be accomplished
simply by forming 2-input ANDs of the decoder outputs with the corresponding data input,and then forming an OR of these terms. Explicitly,

Q = C0D0+ C1D1+C2D2+C3D3

Finally, if an ENABLE line E is included, it is simply ANDed with the righthand side of this expression. This can be used to switch the entire MUX IC off/on, and is useful for expansion to more bits.  

Gate Types and Truth Tables

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The basic logic gates are AND, OR, NAND, NOR, XOR, INV, and BUF. The last two are not standard terms; they stand for \inverter" and \buffer ", respectively.

AND GATE
OR GATE
XOR GATE



Karnaugh Maps

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This section presents a technique for simplifying logical
expressions. It will:

„ Define Karnaugh and establish the correspondence between
Karnaugh maps and truth tables and logical expressions.

„ Show how to use Karnaugh maps to derive minimal sumof-products and product-of-sums expressions.
„ 
Introduce the concept of "don't care" entries and show how
to extend Karnaugh map techniques to include maps with
don't care entries.

Karnaugh Map Definitions

†A Karnaugh map is a two-dimensional truth-table.Unlike ordinary (i.e., one-dimensional) truth tables,however, certain logical network simplifications can be easily recognized from a Karnaugh map.

The interpretation of a type 1 map is that the rows or columns labeled with a variable correspond to region of the map where that variable has value 1.
Exercise: Plot the following expression on a Karnaugh map.
Z = (A•B)⊕(C+D)

Minimal Sum-Of-Products Expressions


†Ordering of Squares

„ The important feature of the ordering of squares is that the
squares are numbered so that the binary representations for
the numbers of two adjacent squares differ in exactly one
position.
‹This is due to the use of a Gray code (one in which adjacent
numbers differ in only one position) to label the edges of a type 2
map.
‹The labels for the type 1 map must be chosen to guarantee this
property.
„
Note that squares at opposite ends of the same row or
column also have this property (i.e., their associated
numbers differ in exactly one position).
For k-variable maps, this reduction technique can also be applied to groupings of 4,8,16,...,2k rectangles all of whose binary numbers agree in (k-2),(k-3),(k-
4),...,0 positions, respectively.

Rules for Grouping:

„ The number of squares in a grouping is 2i for some i such
that 1 ≤ i ≤ k.
„ There are exactly k-i variables that have constant value for
all squares in the grouping.

†Resulting Product Terms:

„ If X is a variable that has value 0 in all of the squares in the
grouping, then the literal X' is in the product term.
„ If X is a variable that has value 1 in all of the squares in the
grouping, then the literal X is in the product term.
„ If X is a variable that has value 0 for some squares in the
grouping and value 1 for others, then neither X' nor X are
in the product term.

In order to minimize the resulting logical expression,
the groupings should be selected as follows:

„ Identify those groupings that are maximal in the sense that
they are not contained in any other possible grouping. The
product terms obtained from such groupings are called
prime implicants.

‹A distinguished 1-cell is a cell that is covered by only one prime
implicant.
‹
An essential prime implicant is one that covers a distiquished 1-
cell.
„
Use the fewest possible number of maximal groupings
needed to cover all of the squares marked with a 1.

†Examples:




Rules for Grouping:

„ Same as for sum-of-products, except that zero's are
grouped instead of ones.

†Resulting Sum Terms:

„ If variable X has value 0 for allsquares in the group, then
the literal X is in the sum term.
„ If variable X has value 1 for all squares in the group, then
the literal X' is in the sum term.
„ If variable X has value 0 for some squares in the group and
value 1 for the others, then that variable does not appear in
the sum term.

†Prime Implicate:

„ Maximal grouping of zeros

QUINE-McCLUSKEY MINIMIZATION Method

Posted by AJ On Thursday, 11 July 2013 0 comments

Quine-McCluskey minimization method uses the same theorem to produce the solution as the K-map method, namely X(Y+Y')=X
Minimization Technique
  • The expression is represented in the canonical SOP form if not already in that form.
  • The function is converted into numeric notation.
  • The numbers are converted into binary form.
  • The minterms are arranged in a column divided into groups.
  • Begin with the minimization procedure.
  • Each minterm of one group is compared with each minterm in the group immediately below.
  • Each time a number is found in one group which is the same as a number in the group below except for one digit, the numbers pair is ticked and a new composite is created.
  • This composite number has the same number of digits as the numbers in the pair except the digit different which is replaced by an "x".
  • The above procedure is repeated on the second column to generate a third column.
  • The next step is to identify the essential prime implicants, which can be done using a prime implicant chart.
  • Where a prime implicant covers a minterm, the intersection of the corresponding row and column is marked with a cross.
  • Those columns with only one cross identify the essential prime implicants. -> These prime implicants must be in the final answer.
  • The single crosses on a column are circled and all the crosses on the same row are also circled, indicating that these crosses are covered by the prime implicants selected.
  • Once one cross on a column is circled, all the crosses on that column can be circled since the minterm is now covered.
  • If any non-essential prime implicant has all its crosses circled, the prime implicant is redundant and need not be considered further.
  • Next, a selection must be made from the remaining nonessential prime implicants, by considering how the non-circled crosses can be covered best.
  • One generally would take those prime implicants which cover the greatest number of crosses on their row.
  • If all the crosses in one row also occur on another row which includes further crosses, then the latter is said to dominate the former and can be selected.
  • The dominated prime implicant can then be deleted.
Example
Find the minimal sum of products for the Boolean expression,
f=clip_image001(1,2,3,7,8,9,10,11,14,15), using Quine-McCluskey method.
Firstly these minterms are represented in the binary form as shown in the table below. The above binary representations are grouped into a number of sections in terms of the number of 1's as shown in the table below.
Binary representation of minterms
Minterms
U
V
W
X
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
11
1
0
1
1
14
1
1
1
0
15
1
1
1
1
Group of minterms for different number of 1's
No of 1's
Minterms
U
V
W
X
1
1
0
0
0
1
1
2
0
0
1
0
1
8
1
0
0
0
2
3
0
0
1
1
2
9
1
0
0
1
2
10
1
0
1
0
3
7
0
1
1
1
3
11
1
0
1
1
3
14
1
1
1
0
4
15
1
1
1
1
Any two numbers in these groups which differ from each other by only one variable can be chosen and combined, to get 2-cell combination, as shown in the table below.
2-Cell combinations
Combinations
U
V
W
X
(1,3)
0
0
-
1
(1,9)
-
0
0
1
(2,3)
0
0
1
-
(2,10)
-
0
1
0
(8,9)
1
0
0
-
(8,10)
1
0
-
0
(3,7)
0
-
1
1
(3,11)
-
0
1
1
(9,11)
1
0
-
1
(10,11)
1
0
1
-
(10,14)
1
-
1
0
(7,15)
-
1
1
1
(11,15)
1
-
1
1
(14,15)
1
1
1
-
From the 2-cell combinations, one variable and dash in the same position can be combined to form 4-cell combinations as shown in the figure below.
Combinations
U
V
W
X
(1,3,9,11)
-
0
-
1
(2,3,10,11)
-
0
1
-
(8,9,10,11)
1
0
-
-
(3,7,11,15)
-
-
1
1
(10,11,14,15)
1
-
1
-
The cells (1,3) and (9,11) form the same 4-cell combination as the cells (1,9) and (3,11). The order in which the cells are placed in a combination does not have any effect. Thus the (1,3,9,11) combination could be written as (1,9,3,11).
From above 4-cell combination table, the prime implicants table can be plotted as shown in table below.
Prime Implicants Table
Prime Implicants
1
2
3
7
8
9
10
11
14
15
(1,3,9,11)
X
-
X
-
-
X
-
X
-
-
(2,3,10,11)
-
X
X
-
-
-
X
X
-
-
(8,9,10,11)
-
-
-
-
X
X
X
X
-
-
(3,7,11,15)
-
-
-
-
-
-
X
X
X
X
-
X
X
-
X
X
-
-
-
X
-
The columns having only one cross mark correspond to essential prime implicants. A yellow cross is used against every essential prime implicant. The prime implicants sum gives the function in its minimal SOP form.
Y = V'X + V'W + UV' + WX + UW